Camera control interface slave device to slave device communication

ABSTRACT

In a shared bus where communications are managed by a master device, direct slave device to slave device (S2S) communications is implemented. A first slave device wanting to communicate with a second slave device may make a S2S communication request to the master device. The request may include a requested number of words that the first slave device wishes to send over the shared bus. The master device may have a current word limit which may vary based upon operating parameters. The master device may deny the request if the requested number of words is greater than the current word limit or if it does not support S2S communications. Denial of the request may also be for other reasons, like activity over the shared bus. If the master device grants the request, the slave device may send the requested number of words to another slave device over the shared bus.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present Application for patent is a divisional of U.S. patentapplication Ser. No. 14/507,179, entitled “Camera Control InterfaceSlave Device to Slave Device Communication” filed Oct. 6, 2014, whichclaims priority to now-expired U.S. Provisional Patent Application No.61/887,895, entitled “Camera Control Interface Slave Device to SlaveDevice Communication” filed Oct. 7, 2013, which applications areassigned to the assignee hereof and are hereby expressly incorporated byreference herein.

FIELD

The present disclosure pertains to enabling operations over a sharedcontrol data bus and, more particularly, to communication of data fromone slave device to another slave device over a multi-wire data and/orclock control data bus.

BACKGROUND

I2C (also referred to as I²C) is a multi-master serial single-endedcontrol data bus used for attaching low-speed peripherals to amotherboard, embedded system, cellphone, or other electronic devices.The I2C control data bus includes a clock (SCL) and data (SDA) lineswith 7-bit addressing. The control data bus has two roles for nodes:master and slave. A master node is a node that generates the clock andinitiates communication with slave nodes. A slave node is a node thatreceives the clock and responds when addressed by the master. The I2Ccontrol data bus is a multi-master control data bus which means anynumber of master nodes can be present. Additionally, master and slaveroles may be changed between messages. I2C defines basic types ofmessages, each of which begins with a START and ends with a STOP.

In this context of a camera implementation, unidirectional transmissionsmay be used to capture an image from a sensor and transmit such imagedata to memory in a baseband processor, while control data may beexchanged between the baseband processor and the sensor as well as otherperipheral devices. In one example, a Camera Control Interface (CCI)protocol may be used for such control data between the basebandprocessor and the image sensor (and/or one or more slave nodes). In oneexample, the CCI protocol may be implemented over an I2C serial controldata bus between the image sensor and the baseband processor.

Master devices control access to the control data bus. While some slavedevices may have the capability of switching to a master mode ofoperation, other slave devices cannot operate in the master mode. Onemajor distinction between a slave-only slave device versus amaster-capable slave device is the ability to receive (e.g., handle)interrupts on an interrupt request line (IRQ). The slave-only slavedevices can cause/send interrupts but cannot handle such interrupts.Therefore, because interrupt handling is extremely important, heretoforeslave devices cannot communicate directly with other slave devices.Accordingly, it would be desirable to enable slave device to slavedevice communications over a shared data bus controlled by a masterdevice.

SUMMARY

A master device is provided comprising a bus interface circuit and aprocessing circuit. The bus interface circuit may serve to couple to acontrol data bus shared with a plurality of slave devices. Theprocessing circuit may be coupled to the bus interface and configuredto: (a) control access to the control data bus by the plurality of slavedevices; and/or (b) receive, a slave device to slave devicecommunication request, from a slave device requesting access to thecontrol data bus.

In one example, the slave device to slave device communication requestmay include a requested number of words to be transferred by therequesting slave device to another slave device.

In another example, the slave device to slave device communicationrequest may include a requested maximum number of words to betransferred from the requesting slave device to another slave deviceover the control data bus. The processing circuit may be furtherconfigured to send, to the requesting slave device, a response grantingthe request. The response grants the request by including a word limitnumber in the response that is equal to or greater than a maximum numberof words specified in the request. The processing circuit may be furtherconfigured to: (a) monitor the control data bus to detect an end ofslave device to slave device communications; and/or (b) regain controlof the control data bus after an end of slave device to slave devicecommunications is detected.

In yet another example, the slave device to slave device communicationrequest may include a requested maximum number of words to betransferred from the requesting slave device to another slave deviceover the control data bus. The processing circuit may be furtherconfigured to send, to the requesting slave device, a response denyingthe request. The slave device to slave device communication request maybe denied if the requested maximum number of words is greater than acurrent word limit of the master device. The processing circuit may befurther configured to send, to the requesting slave device, a responsedenying the request by sending an acceptable number of words when arequested maximum number of words provided by the requesting slavedevice is greater than a current word limit. The master device may alsosend the response denying the request if the master device does notsupport slave device to slave device communications.

A method operational by a master device is provided, comprising: (a)controlling access to a control data bus shared with a plurality ofslave devices; and/or (b) receiving a slave device to slave devicecommunication request from a slave device requesting access to thecontrol data bus. The slave device to slave device communication requestmay include a requested maximum number of words to be transferred fromthe requesting slave device to another slave device over the controldata bus.

The method may further comprise: (a) sending, to the requesting slavedevice, a response granting the request; (b) monitoring the control databus to detect an end of slave device to slave device communications;and/or (c) regaining control of the control data bus after an end ofslave device to slave device communications is detected.

The method may further comprise sending, to the requesting slave device,a response denying the request. In one example, in response to therequest denial, the method may further include: (a) receiving a requestfrom the requesting slave device to have the master device transfer acertain amount of information between the requesting slave device andthe another slave device; and/or (b) transferring data between therequested information between the requesting slave device and theanother slave device. In another example, the response denying therequest may include an acceptable number of words that is less than therequested maximum number of words.

A slave device, comprising a bus interface circuit and a processingcircuit. The bus interface circuit may serve to couple the slave deviceto a control data bus shared with a plurality of slave devices and atleast one master device. The processing circuit may be coupled to thebus interface circuit and configured to send a slave device to slavedevice communication request from the slave device to the master deviceover the control data bus. The communication request may include arequested maximum number of words to be transmitted by the slave deviceto another slave device over the control data bus.

In one example, the processing circuit may be further configured toreceive a response denying the request from the master device. Thedenial response may include an otherwise acceptable number of words fromthe master device.

In another approach to a denial response, the processing circuit may befurther configured to send a new slave device to slave devicecommunication request to the master device, wherein the new slave deviceto slave device communication request includes a new requested maximumnumber of words that is less than or equal to the received acceptablenumber of words.

In yet another alternative approach to a denial response, the processingcircuit may be further configured to send a new request to have themaster device transfer a certain amount of information between therequesting slave device and the another slave device.

In yet another alternative approach to a denial response, the processingcircuit may be further configured to either: (a) resend the same slavedevice to slave device communication request, with the same maximumnumber of words, to the master device at a later time; or (b) send a newslave device to slave device communication request with a second wordlimit that is less than the previous maximum word limit requested butgreater than an acceptable number of words identified by the masterdevice in its denial of the initial request.

In yet another alternative approach to a denial response, the processingcircuit may be further configured to: (a) send a master request to themaster device to transfer control of the control data bus to therequesting slave device; (b) operate as new master of the control databus if the master request is granted by the master device; and/or (c)send a desired amount of data words to another slave device.

In another example, the processing circuit may be further configured to:(a) receive a response granting the request; and/or (b) send a slavedevice to slave device communication to the control data bus.

The slave device to slave device communication may be limited to anacceptable number of words approved by the master device.

According to another aspect, a method operational on a slave device isprovided, comprising: (a) coupling the slave device to a control databus shared with a plurality of slave devices and at least one masterdevice; and/or (b) sending a slave device to slave device communicationrequest from the slave device to the master device over the control databus. The slave device to slave device communication request may includea requested number of words to be transferred by the slave device toanother device over the control data bus. In one example, the method mayfurther comprise: (a) receiving a response granting the request; and/or(b) sending a slave device to slave device communication to the controldata bus. The slave device to slave device communication may be limitedto an acceptable number of words approved by the master device.

SUMMARY OF FIGURES

Various features, nature, and advantages may become apparent from thedetailed description set forth below when taken in conjunction with thedrawings in which like reference characters identify correspondinglythroughout.

FIG. 1 is a block diagram illustrating an exemplary device having abaseband processor and an image sensor and implementing an image databus and a multi-mode control data bus.

FIG. 2 illustrates an exemplary slave to slave communication process.

FIG. 3 conceptually illustrates an exemplary write data word.

FIG. 4 is a block diagram illustrating an exemplary method fortranscoding of data bits into sequential symbols at a transmitter toembed a clock signal within the sequential symbols.

FIG. 5 illustrates an exemplary conversion between transition numbersand sequential symbols.

FIG. 6 illustrates an exemplary conversion from bits to transitionnumbers at a transmitter and then from transition numbers to bits at areceiver.

FIG. 7 illustrates a general example of converting a ternary number(base-3 number) to a binary number, where each T in {T11, T10, . . . T2,T1, T0} is a symbol transition number.

FIG. 8 illustrates an exemplary method for converting a binary number(bits) to a 12 digit ternary number (base-3 number).

FIG. 9 illustrates an example of one possible implementation of thedivision and the modulo operations of FIG. 8, which may be synthesizableby any commercial synthesis tools.

FIG. 10 illustrates an example of a 20-bit region comprising a 19 bitdata region (e.g., bits 0-18) and an additional 20^(th) bit region(e.g., bit 19).

FIG. 11 illustrates that besides the bit 19 being set for numbers2221_2201_2002₃ to 2222_2222_2222₃, that range of numbers can besubdivided into six sections.

FIG. 12 illustrates an exemplary mapping of a portion of the Bit 19mapping of FIG. 11.

FIG. 13 conceptually illustrates a sequence of transmissions over acontrol data bus that may be performed for a slave device to slavedevice communication.

FIG. 14 conceptually illustrates an exemplary slave to slave transferrequest.

FIG. 15 conceptually illustrates a grant command for a slave device toslave device communication protocol.

FIG. 16 conceptually illustrates details of a grant command for a slavedevice to slave device transfer.

FIG. 17 is a block diagram illustrating an exemplary master deviceadapted for slave device to slave device communication.

FIG. 18 illustrates a method operational on a master device tofacilitate slave device to slave device communication.

FIG. 19 is a block diagram illustrating an exemplary slave deviceadapted for slave device to slave device communication.

FIG. 20 illustrates a method operational on a slave device to performslave device to slave device communication.

DETAILED DESCRIPTION

In the following description, specific details are given to provide athorough understanding of the embodiments. However, it will beunderstood by one of ordinary skill in the art that the embodiments maybe practiced without these specific details. For example, circuits maybe shown in block diagrams in order not to obscure the embodiments inunnecessary detail. In other instances, well-known circuits, structures,and techniques may not be shown in detail in order not to obscure theembodiments.

Overview

A first feature provides for direct slave device to slave devicecommunications over a shared control data bus managed by a masterdevice. A first slave device wishing to communicate with a second slavedevice may make a slave device to slave device communication request tothe master device. The request may include a requested number of wordsthat the first slave device wishes to send to the second slave deviceover the shared control data bus managed by the master device. Suchcommunication request may be for a direct transfer (e.g., read or writeoperations) between the first slave device and the second slave devicewhile bypassing the master device (e.g., the data to be transferred isnot managed or sent by the master device). The master device may have acurrent word limit which may vary based upon operating parameters. Forexample, the master device may allow different numbers of words to becommunicated between the slave devices at different times. For instance,during peak control bus use periods, the slave devices may be limited tocommunicating with each other using no more than eight word at a time.There may be times when no slave device to slave device communicationsare allowed (i.e., the current word limit may be zero). Moreover, duringperiods of low control bus use, the current word limit may be 1024words, for example. Consequently, the current word limit may bedynamically adjusted by the master device managing the bus and maychange over time according to control data bus conditions or for anyother desirable reason.

Because the word limit may change dynamically, and a slave device maynot know what the current word limit is, a second feature provides forcommunicating to the salve device the current word limit. For example,the first slave device desiring to communicate with the second slavedevice sends the slave device to slave device communication requestwhich includes a desired number of words to be communicated to thesecond slave device. When the desired number of words is greater thanthe current word limit, the master device sends the first slave device adenial message that includes the current word limit such that the slavecan request to send a smaller message to the second slave device. Themaster device receives this request for a smaller message and sends thefirst slave device a message granting the request. The first slavedevice then sends the message to the second slave device. The masterdevice monitors the message(s) being sent from the first slave device tothe second slave device. Upon detecting an “end” control code being sentfrom the first slave device to the second slave device, the masterdevice knows the communication has ended and regains control of thecontrol data bus exactly as the master device had done prior to grantingthe communication request by the first slave device. Additionally, themaster device may continuously monitor the IRQ line while the firstslave device is communicating with the second slave device. Anyinterrupt requests occurring during the slave device to slave devicecommunication is handled once the slave device to slave devicecommunication has ended. In one feature, the current word limit is notonly variable based upon control data bus traffic but also on recentfrequency of interrupt requests. Consequently, during periods ofrelatively high interrupt requests, the current word limit may be lowerthan periods of relatively low interrupt requests.

Exemplary System for Slave Device to Slave Device Communications

FIG. 1 is a block diagram illustrating a device 102 having a basebandprocessor 104 and an image sensor 106 and implementing an image data bus116 and a multi-mode control data bus 108 in which slave device to slavedevice communications may be enabled as described herein. While FIG. 1illustrates the multi-mode control data bus 108 within a camera device,it should be clear that this control data bus 108 may be implemented invarious different devices and/or systems. Image data may be sent fromthe image sensor 106 to the baseband processor 104 over an image databus 116 (e.g., a high speed differential DPHY link). In one example, thecontrol data bus 108 may be an I2C control data bus comprising twowires, a clock line (SCL) and a serial data line (SDA). The clock lineSCL may be used to synchronize all data transfers over the I2C bus(control data bus 108). The data line SDA and clock line SCL are coupledto all devices 112, 114, and 118 on the I2C bus (control data bus 108).In this example, control data may be exchanged between the basebandprocessor 104 and the image sensor 106 as well as other peripheraldevices 118 via the control data bus 108. In some implementations, theoperating modes over an I2C control data bus may be referred to as acamera control interface (CCI) mode when used for camera applications.

According to one aspect, an improved mode of operation may beimplemented over the multi-mode control data bus 108 to support cameraoperation. This improved mode of operation over an I2C control data busmay be referred to as a camera control interface extension (CCIe) modewhen used for camera applications. In this example, the basebandprocessor 104 includes a master device 112 and the image sensor 106includes a slave device 114, both the master device 112 and slave device114 may operate according to the camera control interface extension(CCIe) mode over the control data bus 108 without affecting the properoperation of other legacy I2C devices coupled to the control data bus108. According to one aspect, this improved mode over the control databus 108 may be implemented without any bridge device between CCIedevices and any legacy I2C slave devices. An interrupt request (IRQ)line/bus 120 couples the slave devices 114 and 118 to the master device112 allowing the slave devices to notify the master device 112 that theslave device 114 and 118 is in need of attention. In other words, theslave device requesting attention pulls the normally high IRQ line low(grounds the IRQ line 120), and the master device responds by firstidentifying which slave device requested the interrupt, and second,polling the slave for an IRQ status. For example, the status may be arequest to perform a slave device to slave device communication.

FIG. 2 illustrates an exemplary slave device to slave devicecommunication process. Similar to FIG. 1, a device may include a sharedcontrol data bus 202 (e.g., CCIe bus) and a separate single-lineinterrupt bus 204 to which a plurality of devices may be coupled. Inthis example, an active/current master device 206 may control/manageaccess to the control data bus 202 by one or more other devices (e.g.,non-active master devices and/or slave devices).

At a first stage 210, a first slave device 208 may wish to initiatecommunications with a second slave device 216. To do this, the firstslave device may issue/send an interrupt signal 218 over the interruptbus 204. The interrupt bus 204 may allow any device coupled to theinterrupt bus 204 to unilaterally issue an interrupt signal over theinterrupt bus 204 so long as no other device is already asserting aninterrupt signal already. In response to sensing or receiving theinterrupt request signal 218, the master device 206 may attempt toascertain the requesting slave device (e.g., the device that issued theinterrupt signal 218). This may be accomplished by the master device 206polling or requesting 220 that each slave device to provide its status.In one example, this may be done by the master device 206 requesting 220the status from each device coupled to control data bus 202 until thefirst slave device 208 that issued the interrupt signal 218 isidentified.

At a second stage 212, in response to receiving the status request 220,the first slave device 208 may send its status 222 which would indicatethat it issued the interrupt 218 and/or that it wishes to perform aslave device to slave device transfer/communication. Such slave deviceto slave device communication request may be for a direct data transfer(e.g., read or write operations) between the first slave device 208 andthe second slave device 216 while bypassing the master device 206 (e.g.,the data to be transferred is not managed or sent by the master device).In one example, the status 222 may be obtained by the master device 206reading information within status registers for the first slave device208.

Upon identifying the first slave device 208 as the issuer of theinterrupt signal and ascertaining the desired service (e.g., use of thecontrol data bus 202 for slave to slave communications), the masterdevice 206 may grant such request by sending a grant indicator 224 viathe interrupt bus 204. At that point, the first slave device 208 hasbeen granted a limited permission to use the control data bus 202 forits own communications with another slave device 216. Note that becausethe master device 206 controls or manages use of the control data bus202 by all devices coupled to the control data bus 202, there is nochance of conflicting use of the control data bus 202 by another device.In one example, the first slave device 208 is granted use of the controldata bus 202 to send or receive a predetermined number of data words.The use of a slave device to slave device communication request isdistinct from transferring control of the control data bus 202 to thefirst slave

At a third stage 214, the first slave device 208 recognizes that themaster device 206 has granted its request and may perform a slave toslave transfer or communication 224. The slave to slave transfer orcommunication 224 may read data from or send data to a second slavedevice 216. After the predetermined number of data words have been sentover the control data bus 202, the master device may regain control anduse of the control data bus 202. The first slave device 208 stopstransmitting over the control data bus 202 after sending and/orreceiving the predetermined number of data words.

Exemplary Communication Protocol Supporting Slave Device to Slave DeviceCommunications

FIG. 3 illustrates an exemplary write data word format. This illustratesthat each data word 300 includes a 16-bit data portion 302, a 2-bitcontrol code 304, a 1-bit error detection constant 310, and a spare bit306. The 16-bit data portion 302 may be segmented into a 14-bit leastsignificant bit portion 312 (located from bits 5 to 18 of the data word300) and a 2-bit most significant bit portion 308 (located from bits 1to 2 of the data word 300). The 1-bit error detection constant 310 mayserve to detect an error on the data word 300 if the value is anythingother than the expected constant (e.g., “0”). In one example, the writedata word 300 may be a CCIe write data word.

A control code table 314 illustrates various possible values for thecontrol code 304. In one example, multiple write data words can be sentsequentially. If the control code of the current write word is ‘00’(symbol C0), then the data is to be written to the previous address. Ifthe control code of the current write word is ‘01’ (symbol C1), then thedata is to be written to the previous address+1. If the control code ofthe current write word is ‘10’ (symbol E), this indicates an end offrame and the next word may be a slave device identifier (SID) or anExit code.

The data word 300 may also have a spare bit 306 (e.g., bit 19, alsoreferred to as 20^(th) bit) that may be used to transmit commands andother information between a master device and one or more slave devices.The spare bit 306 (e.g., bit 19) may be used to encode commands betweendevices coupled to the control data bus 108. A spare bit data regionthat may be defined by the use of this spare bit 306 (e.g., bit 19, alsoreferred to as 20^(th) bit) is further illustrated and discussed inFIGS. 10, 11, and 12.

FIG. 4 is a block diagram illustrating an exemplary method fortranscoding of data bits into sequential symbols at a transmitter toembed a clock signal within the sequential symbols. At the transmitter402, a sequence of data bits 404 are converted into a ternary (base 3)number (e.g., where individual digits of the ternary number are a“transition number”), and the ternary numbers are converted intosequential symbols which are transmitted over a control data bus thatincludes a clock line SCL 412 and a data line SDA 414.

In one example, an original 20-bits 404 of binary data is input to abit-to-transition number converter block 408 to be converted to a12-digits ternary number 409. Each digit of a 12-digits ternary numbermay represent a “transition number”. Two consecutive digits of atransition number may be the same digit value. Each digit of atransition number is converted into a sequential symbol at atransition-to-symbol block 410 such that no two consecutive sequentialsymbols have the same value. Because a transition (e.g., change) isguaranteed at every sequential symbol, such sequential symbol transitionmay serve to embed a clock signal. Each sequential symbol 416 is thensent over a two wire physical link (e.g., I2C control data buscomprising a SCL line 412 and a SDA line 414).

At a receiver 420 the process is reversed to convert the sequentialsymbols back to bits and, in the process, a clock signal is extractedfrom the sequential symbol transition. The receiver 420 receives thesequential symbols 422 over the two wire physical link (e.g., an I2Ccontrol data bus comprising a SCL line 424 and a SDA line 426). Thereceived sequential symbols 422 are input into a clock-data recovery(CDR) block 428 to recover a clock timing and sample the sequentialsymbols (S). A symbol-to-transition number converter block 430 thenconverts each sequential symbol to a transition number, where eachtransition number represents a digit of a ternary number. Then, atransition number-to-bits converter 432 converts twelve (12) transitionnumbers (i.e., a ternary number) to restore twenty (20) bits of originaldata from the 12 digit ternary number.

The technique illustrated herein may be used to increase the link rateof a control data bus 108 (FIG. 1) beyond what the I2C standard controldata bus provides and is referred hereto as CCIe mode. In one example, amaster node/device and/or a slave node/device coupled to the controldata bus 108 may implement transmitters and/or receivers that embed aclock signal within sequential symbol changes/transitions (asillustrated in FIG. 5) in order to achieve higher bit rates over thesame control data bus than is possible using a standard I2C control databus.

FIG. 5 illustrates an exemplary conversion between transition numbers502 and sequential symbols 504. An individual digit of ternary number,base-3 number, also referred to as a transition number, can have one ofthe three (3) possible digits or states, 0, 1, or 2. While the samedigit may appear in two consecutive digits of the ternary number, no twoconsecutive sequential symbols have the same value. The conversionbetween a transition number and a sequential symbol guarantees that thesequential symbol always changes (from sequential symbol to sequentialsymbol) even if consecutive transition numbers are the same.

In one example, the conversion function adds the transition number(e.g., digit of a ternary number) plus 1 to the previous raw sequentialsymbol value. If the addition results in a number larger than 3, itrolls over from 0, then the result becomes the state number or value forthe current sequential symbol.

In a first cycle 506, a previous sequential symbol (Ps) is 1 when afirst transition number (T_(a)) 1 is input, so the first transitionnumber 1 plus 1 is added to the previous sequential symbol (Ps), and theresulting current sequential symbol (Cs) of 3 becomes the currentsequential symbol that is sent to the physical link.

In a second (next) cycle 508, a second transition number (T_(b)) of 0 isinput, and the second transition number 0 plus 1 is added to theprevious sequential symbol (Ps) of 3. Since the result of the addition(0+1+3) equals 4, is larger than 3, the rolled over number 0 becomes thecurrent sequential symbol (Cs).

In a third cycle 510, a third transition number (T_(a)) of 0 is input.The conversion logic adds the third transition number 0 plus 1 to theprevious sequential symbol (Ps) 0 to generate current sequential symbol(Cs) 1.

In a fourth cycle 512, a fourth transition number (T_(d)) of 2 is input.The conversion logic adds the fourth transition number (T_(d)) 2 plus 1to the previous symbol (Ps) 1 to generate current sequential symbol (Cs)0 (since the result of the addition, 4, is larger than 3, the rolledover number 0 becomes the current sequential symbol).

Consequently, even if two consecutive ternary digits T_(b) and T_(c)have the same number, this conversion guarantees that two consecutivesequential symbols have different state values. Because of thisconversion, the guaranteed sequential symbol change or transition in thesequence of symbols 504 may serve to embed a clock signal, therebyfreeing the clock line SCL in an I2C control data bus for datatransmissions.

Note that while this example of transition number to sequential numberconversions adds a guaranteed number “1” to increment betweenconsecutive sequential symbols, other values may be used in otherimplementations to guarantee a transition or change between sequentialsymbols.

Referring again to FIG. 4, at the receiver 420 the process illustratedin FIG. 5 is reversed to convert the sequential symbols back to bitsand, in the process, a clock signal is extracted from the symboltransition. The receiver 420 receives sequential symbols 422 over thetwo wire physical link (e.g., I2C bus comprising a SCL line 424 and aSDA line 426). The received sequential symbols 422 are input into aclock-data recovery (CDR) block 428 to recover a clock timing and samplethe transcoded symbols (S). A symbol-to-transition number converterblock 430 then converts each sequential symbol to a transition number,i.e., which makes up a digit within a ternary number. Then, a transitionnumber-to-bits converter 32 converts 12 transition numbers (i.e., aternary number) to restore 20 bits of original data from the 12 digitternary number.

FIG. 6 illustrates an exemplary conversion from bits to transitionnumbers at a transmitter 602 and then from transition numbers to bits ata receiver 604. This example illustrates the transmission for a 2-wiresystem using 12 transition symbols. The transmitter 602 feeds binaryinformation, Bits, into a “Bits to 12×T” converter 606 to generate 12symbol transition numbers, T0 to T11. The receiver 604 receives 12symbols transition numbers, T0 to T11, which are fed into a “12×T toBits” converter 608 to retrieve the binary information (Bits). If thereare r possible symbol transition states per one T, T0 to T11, 12transitions can send r¹² different states. For a 2-wire bus, r=2²−1.Consequently, transitions T0 . . . T11 contain data that can have(2²−1)¹² different states. Consequently, r=4−1=3 and the number ofstates=(4−1)̂12=531441.

In this example for a 2-wire system using 12 symbol transition numbers,it may be assumed that the possible symbol transitions per one T, r is 3(=2²−1). If the number of symbols in a group is 12, a 12-digit ternarynumber (base-3 number): T11, T10, . . . , T2, T1, T0, where each Ti: 0,1, 2, may be used. For example, for {T11, T10, . . . T2, T1, T0}={2, 1,0, 0, 1, 1, 0, 1, 0, 1, 2, 1}, the ternary number is:

2100_1101_0121₃(Ternary  number) = 2 × 3¹¹ + 1 × 3¹⁰ + 0 × 3⁹ + 0 × 3⁸ + 1 × 3⁷ + 1 × 3⁶ + 0 × 3⁵ + 1 × 3⁴ + 0 × 3³ + 1 × 3² + 2 × 3¹ + 1 × 3⁰ = 416356  (0x 65A 64).

In this manner, 12 transitions numbers may be converted into a number.Note that the ternary number 2100_1101_0121₃ may be used as thetransition number, for example, in FIG. 4, so that each transitionnumber (e.g., digit of a ternary number) may be mapped to a sequentialsymbol and vice versa.

The example illustrated in FIG. 6 for a 2-wire system and 12 symboltransition numbers may be generalized to a n-wire system and m symboltransition numbers. If there are r possible symbol transition states perone T, T0 to Tm−1, m transitions can send r^(m) different states, i.e.,r=2^(n)−1. Consequently, transitions numbers T0 . . . Tm−1 contain datathat can have (2^(n)−1)^(m) different states (e.g., sequential numbers).

FIG. 7 illustrates a general example of converting a ternary number(base-3 number) to a binary number, where each T in {T11, T10, . . . T2,T1, T0} is a transition number.

FIG. 8 illustrates an exemplary method for converting a binary number(bits) to a 12 digit ternary number (base-3 number). Each digit of theternary number can be calculated by dividing the remainder (result of amodulo operation) from a higher digit calculation with 3 to the power ofthe digit number, discarding decimal points numbers.

FIG. 9 illustrates an example of one possible implementation of thedivision and the modulo operations of FIG. 8, which may be synthesizableby any commercial synthesis tools.

FIG. 10 conceptually illustrates a bit 19 (the 20^(th) bit or “sparebit” 306 in FIG. 3) is mostly unused in the CCIe protocol and may beused to enable slave device to slave device communications. Morespecifically, FIG. 10 illustrates the bit 19 (i.e., the 20^(th) bit whenthe bit count starts at the first bit being bit 0). In other words, asis typical in the computer sciences, counting bit wise begins at zero,and bit 19 is the 20^(th) bit. Here, the bits 0-18 are representedwithin the ternary number range of 0000_0000_0000₃ to 2221_2201_2001₃.The ternary numbers in the range of 2221_2201_2002₃ to 2222_2222_2222₃are unused. Consequently, the ternary number range 2221_2201_2002₃ to2222_2222_2222₃ may be used to represent bit 19 (i.e., 20^(th) bit). Inother words, 2221_2201_2002₃ ternary is 10,000,000,000,000,000,000binary (0x80000 hexadecimal) and 2222_2222_2222₃ ternary (0x81BF0) isthe largest 12 digit ternary number possible. In one implementation ofslave device to slave device communication, the 20^(th) bit (bit 19) isutilized as described herein.

FIG. 11 conceptually illustrates a CCIe Bit 19 mapping protocol forternary numbers 0000_0000_0000₃ to 2222_2222_2222₃. Note that differenttypes of commands may be encoded within the bit 19 region (e.g., 20^(th)Bit).

FIG. 12 illustrates an exemplary mapping of a portion of the Bit 19mapping of FIG. 11.

FIG. 13 conceptually illustrates a sequence of transmissions over acontrol data bus that may be performed for a slave device to slavedevice communication. In this example, the slave device to slave devicecommunication protocol utilizes the range from 2222_2112_1122₃ to2222_2202_2120₃. The slave device may send an interrupt signal to themaster device over the separate interrupt bus/line. In response to suchinterrupt signal 1301, the master device may initiate/send an IRQinquiry 1303 over the control data bus which causes the requesting slavedevice (S1) to respond 1304. The master device may then read the status1305 of the requesting slave device (S1) in which a slave-to-slavecommunication request 1306 is indicated. This slave-to-slavecommunication request 1306 may include an upper limit (max limit) ofwords for the requested transmission to another slave device. The numberof words may not just be the data portion of the message but rather mayinclude the entire number of words to be transmitted between slavedevices, including all overhead and/or envelope information such as aslave identifier (SID), a cyclic redundancy check or checksum (CRC)and/or synchronization (SYNC) information. The master device, aftergranting 1308 a slave device's request then monitors the slave device'stransmissions 1310 and after an end code is sent from the transmittingslave device, the master device resumes control over the control databus. In other words, the master device monitors the control data bus todetect an end of the granted access, after notifying the slave devicethat sent the request, that the request is granted. Note that duringthis slave to slave transmission frame 1310, the requesting slave devicemay send write commands 1312 and/or read commands 1314 to another slavedevice.

FIG. 14 conceptually illustrates an exemplary slave to slave transferrequest. This exemplary slave to slave transfer request 1403 may beembedded with a portion 1402 of the bit 19 mapping illustrated in FIGS.11 and 12 (e.g., utilizes the range from 2222_2112_1122₃ to2222_2202_2120₃). One example of the slave to slave transfer request1403 is defined by a first bit sequence 1404 in conjunction with twotables 1406 and 1408. This slave to slave transfer request 1403 mayinclude the number of words 1408 to be transmitted over the control databus during the slave to slave transfer.

FIG. 15 conceptually illustrates a grant command for a slave device toslave device communication protocol. In this example, the slave deviceto slave device communication protocol 1502 utilizes the range from2222_2112_1122₃ to 2222_2202_2120₃ in sending request grants and/ordenials. The master device grants the slave device to slave devicecommunication request by returning to the requesting slave device amessage including the same word limit number in the slave device toslave device communication request originally sent from the slave deviceto the master device. Alternatively, the master device returns a wordlimit number smaller than the requested number which the slave deviceunderstands to be a denial of the original request and a furnishing of anew word limit. When the new (i.e., current) word limit is zero, theslave device knows that slave device to slave device communication iscurrently disabled and waits a pre-programmed amount of time beforemaking a second request. Else, if the returned current word limit isnon-zero, the slave device then breaks the original too long messageinto a plurality of messages no larger than the returned current wordlimit. Additionally, in some embodiments, one or more slave devices mayhave a sleep mode to save energy, and when an intended recipient of aslave device to slave device communication is in the sleep mode, themaster device may wake up the sleeping slave device prior to granting arequesting slave device's communication request. Alternatively, themaster device may first deny the requesting slave device's communicationrequest by sending a current word limit of zero and then wakes up thesleeping slave. After a pre-programmed period of time, the denied slavedevice initiates a second request that the master device may now grant.

One example of the slave to slave transfer grant 1503 is defined by afirst bit sequence 1504 in conjunction with two tables 1506 and 1508.This slave to slave transfer grant 1503 may include the number of words1508 allowed to be transmitted over the control data bus during theslave to slave transfer.

FIG. 16 conceptually illustrates details of a grant command for a slavedevice to slave device transfer. In this example, the master device maysend a frame 1602 that includes the requesting slave device's identifier(SID), and extra words 1606. As part of the “address” field, the masterdevice may provide the slave device to slave device grant 1608.

Exemplary Master Device and Method Operational Therein

FIG. 17 is a block diagram illustrating an exemplary master deviceadapted for slave device to slave device communication. The masterdevice 1702 may include a first communication interface/circuit 1706, asecond communication interface/circuit 1708, and/or a processing circuit1704. The first communication interface/circuit 1706 may serve to coupleto a single line interrupt request (IRQ) bus to which a plurality ofother devices may be coupled. The second communication interface/circuit1708 may serve to couple to a control data bus to which the plurality ofother devices may also be coupled.

The processing circuit 1704 may include various sub-circuits and/ormodules to carry out one or more functions described herein. Forexample, a communication management circuit/module 1710 may be adaptedto manage communications over the data bus for all devices coupled tothe control data bus based on interrupt signals asserted over the IRQbus. An IRQ bus monitoring circuit/module 1712 may be adapted to monitorthe IRQ bus to ascertain when an IRQ signal has been asserted (e.g., bya slave device). A slave-to-slave communication grant/denycircuit/module 1714 may be adapted to respond (e.g., grant or deny) to arequest by a slave device to communicate directly with another slavedevice over the control data bus. A data bus monitoring circuit/module1716 may be adapted to allow the master device to monitor the controldata bus to ascertain when the slave-to-slave communications have ended.

FIG. 18 illustrates a method 1800 operational on a master device tofacilitate slave device to slave device communication. The method 1800includes having a master device control/manage access to a control databus shared with a plurality of slave devices 1802. The master device mayreceive a slave device to slave device communication/transfer requestfrom a slave device requesting access to the control data bus 1804. Theslave device to slave device communication/transfer request may includea maximum number of words that the requesting slave device wishes totransmit over the control date bus. In response to such request, themaster device may send, to the requesting slave device, a responsedenying the request by sending an acceptable maximum number of wordswhen a requested maximum number of words is greater than a currentmaximum word limit 1806. For instance, the acceptable number of wordsmay be equal to the current maximum word limit (maintained by the masterdevice) and/or it may be a number less than the requested maximum numberof words. Alternatively, the master device may send, to the requestingslave device, a response granting the request 1808. Moreover, the masterdevice may monitor the control data bus to detect an end of the grantedaccess to the requesting slave device 1810. Upon detection of an end ofslave device to slave device communications over the shared control busis detected, the master device may regain control of the control databus.

In one example, the response from the master device grants the requestby including a word limit number in the response that is equal to orgreater than a maximum number of words specified in the request. Thatis, if the response includes a word limit number that matches therequested maximum number of words specified by the requesting slavedevice or is greater than the requested maximum number of words, therequesting slave device may recognize this as a grant of the request.

According to another aspect, if the master device does not support slavedevice to slave device communications, the master device respond to therequest with a word limit number of zero (0) in its response. Hence, ifa master device may be required (e.g., by a protocol standard) to replyto the slave device to slave device communication request, but it maydeny the request by including a word limit number of zero (0). For thisreason, it may be advisable for master devices that support slave deviceto slave device communications to reply with a non-zero word limitnumber in its response.

According to one aspect, if the master device denies the slave device toslave device communication request, the slave device may wait someamount of time and then resends the same slave device to slave devicecommunication request (e.g., same desired number of words to betransferred) to the master device over the control data bus. Note thatthe original denial may have been due to a busy control data bus, soretrying at a later time may result in the request being granted.Additionally, the slave device may retry sending the same requestseveral times before giving up.

According to another aspect, if the master device denies the slavedevice to slave device communication request, the slave device mayresend the request but with a lower maximum number of words to betransferred by the requesting slave device over the control data bus. Insome implementations, the slave device may breakup a data transfer thatis larger than the maximum number of words permitted by the masterdevice into multiple slave device to slave device communicationrequests.

In an alternative approach, if the master device denies the slave deviceto slave device communication request, but the slave device cannotbreakup the data transfer into multiple portions, the slave device mayrequest the master device to take over the data transfer between therequesting slave device and another slave device.

Exemplary Slave Device and Method Operational Therein

FIG. 19 is a block diagram illustrating an exemplary slave deviceadapted to perform slave device to slave device communication. The slavedevice 1902 may include a first communication interface/circuit 1906, asecond communication interface/circuit 1908, and/or a processing circuit1904. The first communication interface/circuit 1906 may serve to coupleto a single line interrupt request (IRQ) bus to which a plurality ofother devices may be coupled. The second communication interface/circuit1908 may serve to couple to a control data bus to which the plurality ofother devices may also be coupled.

The processing circuit 1904 may include various sub-circuits and/ormodules to carry out one or more functions described herein. Forexample, an interrupt (IRQ) generator circuit/module 1910 may be adaptedto generate an interrupt request over the interrupt bus. Aslave-to-slave communication requesting circuit/module 1912 may beadapted to request use of the control data bus from a master device inorder to perform slave-to-slave communications directly with anotherslave device. A slave-to-slave communication transmission circuit/module1914 may be adapted to send slave-to-slave communications over thecontrol data bus.

FIG. 20 illustrates a method 2000 operational on a slave device tofacilitate slave device to slave device communication. The method 2000includes coupling the slave device to a control data bus shared with aplurality of slave device and managed by a master device 2002. The slavedevice may send a slave device to slave device communication request tothe master device over the control data bus 2004. In response to therequest, the slave device may receive a response denying the requestthat includes an otherwise acceptable maximum number of words from themaster device 2006. If the request is initially denied, the slave devicemay simply wait an amount of time and resend the same initial request.Alternatively, the slave device may send a new slave device to slavedevice communication request including a requested maximum number ofwords less than or equal to the received acceptable maximum number ofwords to the master device 2008.

The slave device may receive a response granting the request from themaster device 2010. Upon receiving the grant response from the masterdevice, the slave device may transmit information to a second slavedevice over the control data bus in, at most, the request number ofwords 2012.

According to one aspect, if the master device denies the slave device toslave device communication request, the slave device may wait someamount of time and then resends the same slave device to slave devicecommunication request (e.g., same desired number of words to betransferred) to the master device over the control data bus. Note thatthe original denial may have been due to a busy control data bus, soretrying at a later time may result in the request being granted.Additionally, the slave device may retry sending the same requestseveral times before giving up.

According to another aspect, if the master device denies the slavedevice to slave device communication request, the slave device mayresend the request but with a lower maximum number of words to betransferred by the requesting slave device over the control data bus. Insome implementations, the slave device may breakup a data transfer thatis larger than the maximum number of words permitted by the masterdevice into multiple slave device to slave device communicationrequests.

In an alternative approach, if the master device denies the slave deviceto slave device communication request, but the slave device cannot breakup the data transfer into multiple portions, the slave device mayrequest the master device to take over the data transfer between therequesting slave device and another slave device.

In yet another approach, if the master device denies the slave device toslave device communication request and the requesting slave device iscapable of operating in either master mode or slave mode, the requestingslave device may request to become the master of the shared control databus in order to transfer the desired number of words.

One or more of the components, steps, features, and/or functionsillustrated in the Figures may be rearranged and/or combined into asingle component, step, feature, or function or embodied in severalcomponents, steps, or functions. Additional elements, components, steps,and/or functions may also be added without departing from novel featuresdisclosed herein. The apparatus, devices, and/or components illustratedin the Figures may be configured to perform one or more of the methods,features, or steps described in the Figures. The novel algorithmsdescribed herein may also be efficiently implemented in software and/orembedded in hardware.

In addition, it is noted that the embodiments may be described as aprocess that is depicted as a flowchart, a flow diagram, a structurediagram, or a block diagram. Although a flowchart may describe theoperations as a sequential process, many of the operations can beperformed in parallel or concurrently. In addition, the order of theoperations may be re-arranged. A process is terminated when itsoperations are completed. A process may correspond to a method, afunction, a procedure, a subroutine, a subprogram, etc. When a processcorresponds to a function, its termination corresponds to a return ofthe function to the calling function or the main function.

Moreover, a storage medium may represent one or more devices for storingdata, including read-only memory (ROM), random access memory (RAM),magnetic disk storage mediums, optical storage mediums, flash memorydevices, and/or other machine-readable mediums for storing information.The term “machine readable medium” includes, but is not limited toportable or fixed storage devices, optical storage devices, wirelesschannels and various other mediums capable of storing, containing, orcarrying instruction(s) and/or data.

Furthermore, embodiments may be implemented by hardware, software,firmware, middleware, microcode, or any combination thereof. Whenimplemented in software, firmware, middleware, or microcode, the programcode or code segments to perform the necessary tasks may be stored in amachine-readable medium such as a storage medium or other storage(s). Aprocessor may perform the necessary tasks. A code segment may representa procedure, a function, a subprogram, a program, a routine, asubroutine, a module, a software package, a class, or any combination ofinstructions, data structures, or program statements. A code segment maybe coupled to another code segment or a hardware circuit by passingand/or receiving information, data, arguments, parameters, or memorycontents. Information, arguments, parameters, data, etc. may be passed,forwarded, or transmitted via any suitable means including memorysharing, message passing, token passing, network transmission, etc.

The various illustrative logical blocks, modules, circuits, elements,and/or components described in connection with the examples disclosedherein may be implemented or performed with a general purpose processor,a digital signal processor (DSP), an application specific integratedcircuit (ASIC), a field programmable gate array (FPGA) or otherprogrammable logic component, discrete gate or transistor logic,discrete hardware components, or any combination thereof designed toperform the functions described herein. A general purpose processor maybe a microprocessor, but in the alternative, the processor may be anyconventional processor, controller, microcontroller, or state machine. Aprocessor may also be implemented as a combination of computingcomponents, e.g., a combination of a DSP and a microprocessor, a numberof microprocessors, one or more microprocessors in conjunction with aDSP core, or any other such configuration.

The methods or algorithms described in connection with the examplesdisclosed herein may be embodied directly in hardware, in a softwaremodule executable by a processor, or in a combination of both, in theform of processing unit, programming instructions, or other directions,and may be contained in a single device or distributed across multipledevices. A software module may reside in RAM memory, flash memory, ROMmemory, EPROM memory, EEPROM memory, registers, hard disk, a removabledisk, a CD-ROM, or any other form of storage medium known in the art. Astorage medium may be coupled to the processor such that the processorcan read information from, and write information to, the storage medium.In the alternative, the storage medium may be integral to the processor.

Those of skill in the art would further appreciate that the variousillustrative logical blocks, modules, circuits, and algorithm stepsdescribed in connection with the embodiments disclosed herein may beimplemented as electronic hardware, computer software, or combinationsof both. To clearly illustrate this interchangeability of hardware andsoftware, various illustrative components, blocks, modules, circuits,and steps have been described above generally in terms of theirfunctionality. Whether such functionality is implemented as hardware orsoftware depends upon the particular application and design constraintsimposed on the overall system.

The various features of the invention described herein can beimplemented in different systems without departing from the invention.It should be noted that the foregoing embodiments are merely examplesand are not to be construed as limiting the invention. The descriptionof the embodiments is intended to be illustrative, and not to limit thescope of the claims. As such, the present teachings can be readilyapplied to other types of apparatuses and many alternatives,modifications, and variations will be apparent to those skilled in theart.

What is claimed is:
 1. A master device, comprising: a bus interfacecircuit to couple to a control data bus shared with a plurality of slavedevices; and a processing circuit coupled to the bus interface circuitand configured to: control access to the control data bus by theplurality of slave devices; receive a request from a slave device foraccess to the control data bus for slave device to slave devicecommunication; grant or deny the request received from the slave device;and after granting the request, permit the slave to use the control databus for direct data transfer between the slave device and another slavedevice of the plurality of slave devices, without transmitting the datatransferred during the direct data transfer.
 2. The master device ofclaim 1, wherein the slave device to slave device communication requestincludes a requested number of words to be transferred by the requestingslave device to another slave device.
 3. The master device of claim 1,wherein the slave device to slave device communication request includesa requested maximum number of words to be transferred from therequesting slave device to another slave device over the control databus; and the processing circuit is further configured to: send, to therequesting slave device, a response granting the request.
 4. The masterdevice of claim 3, wherein the response grants the request by includinga word limit number in the response that is equal to or greater than themaximum number of words included in the request.
 5. The master device ofclaim 3, wherein the processing circuit is configured to: monitor thecontrol data bus to detect an end of slave device to slave devicecommunications; and regain control of the control data bus after an endof slave device to slave device communications is detected.
 6. Themaster device of claim 1, wherein the slave device to slave devicecommunication request includes a requested maximum number of words to betransferred from the requesting slave device to another slave deviceover the control data bus; and the processing circuit is furtherconfigured to: send, to the requesting slave device, a response denyingthe request.
 7. The master device of claim 6, wherein the slave deviceto slave device communication request is denied if the requested maximumnumber of words is greater than a current word limit of the masterdevice.
 8. The master device of claim 6, wherein the processing circuitis further configured to: send, to the requesting slave device, aresponse denying the request by sending an acceptable number of wordswhen the requested maximum number of words provided by the requestingslave device is greater than a current word limit.
 9. The master deviceof claim 6, wherein the master device sends the response denying therequest if the master device does not support slave device to slavedevice communications.
 10. A method operational by a master device,comprising: controlling access to a control data bus shared with aplurality of slave devices; receiving a request from a slave device foraccess to the control data bus for slave device to slave devicecommunication; granting or denying the request from the slave device;and after granting the request, permitting the slave to use the controldata bus for direct data transfer between the slave device and anotherslave device of the plurality of slave devices, without transmitting thedata transferred during the direct data transfer.
 11. The method ofclaim 10, wherein the slave device to slave device communication requestincludes a requested maximum number of words to be transferred from therequesting slave device to another slave device over the control databus.
 12. The method of claim 11, further comprising: sending, to therequesting slave device, a response granting the request.
 13. The methodof claim 12, further comprising: monitoring the control data bus todetect an end of slave device to slave device communications; andregaining control of the control data bus after an end of slave deviceto slave device communications is detected.
 14. The method of claim 11,further comprising: sending, to the requesting slave device, a responsedenying the request.
 15. The method of claim 14, further comprising:receiving a request from the requesting slave device to have the masterdevice transfer a certain amount of information between the requestingslave device and the another slave device; and transferring data betweenthe requested information between the requesting slave device and theanother slave device.
 16. The method of claim 14, wherein the responsedenying the request includes an acceptable number of words that is lessthan the requested maximum number of words.
 17. A slave device,comprising: a bus interface circuit to couple to a control data busshared with a plurality of slave devices and a master device; and aprocessing circuit coupled to the bus interface circuit and configuredto: send a slave device to slave device communication request over thecontrol data bus to the master device; receive a response granting ordenying the request from the master device; and after receiving aresponse granting the request, use the control data bus for direct datatransfer between the slave device and another slave device of theplurality of slave devices in which data is transferred between theslave device and another slave device without being transmitted by themaster device.
 18. The slave device of claim 17, wherein thecommunication request includes a requested maximum number of words to betransmitted by the slave device to another slave device over the controldata bus.
 19. The slave device of claim 18, wherein the processingcircuit is further configured to: receive a response denying the requestfrom the master device.
 20. The slave device of claim 19, wherein theresponse includes an otherwise acceptable number of words from themaster device.
 21. The slave device of claim 20, wherein the processingcircuit is further configured to: send a new slave device to slavedevice communication request to the master device, wherein the new slavedevice to slave device communication request includes a new requestedmaximum number of words that is less than or equal to the acceptablenumber of words.
 22. The slave device of claim 19, wherein theprocessing circuit is further configured to: send a new request to havethe master device transfer a certain amount of information between therequesting slave device and the another slave device.
 23. The slavedevice of claim 19, wherein the processing circuit is further configuredto either: resend the same slave device to slave device communicationrequest, with the same maximum number of words, to the master device ata later time; or send a new slave device to slave device communicationrequest with a second word limit that is less than the previous maximumword limit requested but greater than an acceptable number of wordsidentified by the master device in its denial of the initial request.24. The slave device of claim 19, wherein the processing circuit isfurther configured to: send a master request to the master device totransfer control of the control data bus to the requesting slave device;operate as new master of the control data bus if the master request isgranted by the master device; and send a desired amount of data words toanother slave device.
 25. The slave device of claim 17, wherein theprocessing circuit is further configured to: receive the responsegranting the request; and send a slave device to slave devicecommunication to the control data bus.
 26. The slave device of claim 17,wherein the slave device to slave device communication is limited to anacceptable number of words approved by the master device.
 27. A methodoperational on a slave device coupled to a control data bus shared witha plurality of slave devices and a master device, comprising: sending aslave device to slave device communication request over the control databus to the master device; receiving a response granting or denying therequest from the master device; and after receiving a response grantingthe request, using the control data bus for direct data transfer betweenthe slave device and another slave device of the plurality of slavedevices in which data is transferred between the slave device andanother slave device without being transmitted by the master device. 28.The method of claim 27, wherein the slave device to slave devicecommunication request includes a requested number of words to betransferred by the slave device to another device over the control databus.
 29. The method of claim 27, further comprising: receiving theresponse granting the request; and sending a slave device to slavedevice communication to the control data bus.
 30. The method of claim29, wherein the slave device to slave device communication is limited toan acceptable number of words approved by the master device.